1. Field of the Invention
The present invention relates to the structure of a bipolar transistor to be used in a semiconductor device requiring high integration such as a memory LSI formed of a bipolar/CMOS combination integrated circuit (BiCMOS circuit).
2. Description of the Related Art
There is arranged a BiCMOS logic gate as shown in FIG. 1 at a position adjacent to a memory cell array in a memory LSI. A p channel MOS transistor 21 or an N channel MOS transistor 22 is operated by a control signal S1 sent from a decoder (not shown). Due to this, the voltage of a word line WL is pulled up or pulled down by a bipolar transistor 23 or 24 of the output stage. CW is a load capacity of the word line WL.
FIG. 2A is a plane view showing the structure of one bipolar transistor 23 in the BiCMOS logic gate of FIG. 1 driving the word line WL. This is a portion enclosed with a broken line 25. FIG. 2B is a cross sectional view along a line 2B--2B of FIG. 2A. On a bury N.sup.+ type region 32 formed in a silicon substrate 31, there is formed an N.sup.- type collector region 33 whose concentration is lower than concentration of the N.sup.+ type region 32. On the surface of the collector region 33, there are formed a diffusion region 34 for taking out a collector, a P.sup.- type intrinsic base region 35, a P.sup.+ type external base region 36 whose concentration is higher than concentration of the P.sup.- type region 35 and a N.sup.+ type emitter region 37. A field insulating film 39 is formed in the periphery of a transistor region 38. An interlayer insulating film 40 is formed to cover the transistor region 38 and the field insulating film 39. Contract holes 41 are formed in the surface of the interlayer insulating film 40, and a collector electrode 42, a base electrode 43 and an emitter electrode 44 are respectively formed in the holes. The emitter electrode 44 is connected to the word line WL. In other words, one bipolar transistor is formed for a pitch MP 1 of a memory cell 45 in the memory cell region extending to the word line WL. Or, as shown in FIG. 3, a 1/2 bipolar transistor is formed for a pitch MP 2 of a memory cell 46. In FIG. 3, the emitter electrode 44 is connected to two word lines.
The respective electrodes 42, 43, and 44 of the bipolar transistors are directly taken out of the respective active regions 34, 36, and 37 through the contact holes 41. The shape of the metal of the emitter electrode 44 and the base electrode 43 and that of the contact hole, which are brought into contact with an active region 37 of a substrate 31 to an active region 36, are rectangular, and the directions of the long sides are parallel to each other. The arrangement is made such that the long sides are perpendicular to a line 2B--2B passing the centers of the above rectangular shapes. The above arrangement makes it possible to uniform a distance where the emitter electrode 44 of the bipolar transistor is connected to the base electrode 43 through the active region. Moreover, the distance can be minimized, so that a parasitic resistance in the emitter region 37 and the base region 36 can be considerably controlled.
According to the above-mentioned structure, the area of transistor size Td is largely occupied by the contact size of the metal of each electrode, a joint allowance between the contact and the metallic wires, and the sum (4a+2b+c) of the minimum working size between the wires.
In accordance with increase in the memory capacity and decrease in the working size, the memory size is increasingly made small. Due to this, in the size Td of the above-structured bipolar transistor including the element separation region, it is difficult to reduce the size of the bipolar transistor corresponding to the memory size. In other words, if the memory cell is much more reduced, the bipolar transistor functioning as a driver must drive the word lines which are more than two. Due to this, the capacities of the word lines increase, and this prevents the high speed operation of the memory.
As mentioned above, in the conventional device, one to 1/2 bipolar transistor functioning as a driver is formed for the pitch of the memory cell to be adjacent to the memory cell array. However, the conventional working size cannot deal with the reduction of the memory size.